MAX15001 データシートの表示（PDF） - Maxim Integrated

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MAX15001

Current-Mode PWM Controllers with Programmable Switching Frequency

Maxim Integrated 

Current-Mode PWM Controllers with

Programmable Switching Frequency

threshold), then startup has been accomplished and

sustained operation will commence. If VIN drops below

9.74V before startup is complete, the device goes back

to low-current UVLO. In this case, increase the value of

C1 to store enough energy to allow for the voltage at

the tertiary winding to build up.

MAX15000 fig02

VCC

2V/div

VIN

5V/div

0V

100ms/div

Figure 2. VIN and VCC During Startup When Using the

MAX15000 in Bootstrapped Mode (Figure 1)

UVLO Flag (UFLG)

The MAX15000/MAX15001 have an open-drain under-

voltage flag output (UFLG). When used with an opto-

coupler the UFLG output can serve to sequence a

secondary-side controller. An internal 210µs delay

occurs the instant the voltage on UVLO/EN drops

below 1.17V until NDRV stops switching. This allows for

the UFLG output to change state before the MAX15000/

MAX15001 shut down (Figure 3).

When the voltage at the UVLO/EN is above the thresh-

old, UFLG is high impedance. When UVLO/EN is below

the threshold, UFLG goes low. UFLG is not affected by

bootstrap UVLO (MAX15000).

Soft-Start

The MAX15000/MAX15001 soft-start feature allows the

output voltage to ramp up in a controlled manner, elimi-

nating voltage overshoot. The MAX15000/MAX15001

reference generator that is internally connected to the

error amplifier soft-starts to achieve superior control of

the output voltage under heavy and light load condi-

tions. Soft-start begins after UVLO is deasserted (VIN is

above 21.6V for the MAX15000, VIN is above 9.5V for

the MAX15001, and the voltage on UVLO/EN is above

1.23V). The voltage applied to the noninverting node of

the amplifier ramps from 0 to 1.23V in 1984 NDRV

switching cycles. Use the following formula to calculate

the soft-start time (tSS):

tSS

=

1984

fNDRV

where fNDRV is the switching frequency at the NDRV

output. Figure 4 shows the soft-start regulated output of

a power supply using the MAX15000 during startup.

VUVLO/EN

VUFLG

1.23V

(±1%)

LOW

VNDRV

SHUTDOWN

Hi-Z

3µs

tEXTR

3ms

1.17V (typ)

0.6µs

NDRV SWITCHING

LOW

tEXTF

210µs

SHUTDOWN

Figure 3. UVLO/EN and UFLG Operation Timing

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