MAX1951ESA データシートの表示（PDF） - Maxim Integrated

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MAX1951ESA

1MHz, All-Ceramic, 2.6V to 5.5V Input, 2A PWM Step-Down DC-to-DC Regulators

Maxim Integrated 

1MHz, All-Ceramic, 2.6V to 5.5V Input,

2A PWM Step-Down DC-to-DC Regulators

gmc = 4.2S

fSWITCH = 1MHz

RLOAD = VOUT/IOUT(MAX) = 1.5V/1.5 A = 1Ω

fpMOD = [1/(2π x COUT x (RLOAD + RESR)]

= [1/(2 x π ×10 ×10-6 x (1 + 0.01)] = 15.76kHz.

fzESR = [1/(2π xCOUT RESR)]

= [1/(2 x π × 10 ×10-6 × 0.01)] = 1.59MHz.

For 2µH output inductor, pick the closed-loop unity-gain

crossover frequency (fC) at 200kHz. Determine the

power modulator gain at fC:

GMOD(fc) = gmc × RLOAD × fpMOD/fC = 4.2 × 1 ×

15.76kHz/200kHz = 0.33

then:

R1 = VO x K/(gmEA x VFB x GMOD(fc)) = (1.5 x 0.55)/

(60 ×10-6 × 0.8 × 0.33) ≈ 51.1kΩ (1%)

C2 = (VOUT × COUT)/(R × IOUT(max) )

= (1.5 × 10 × 10-6)/(51.1k × 1.5)

≈ 196pF, choose 220pF, 10%

Applications Information

PCB Layout Considerations

Careful PCB layout is critical to achieve clean and sta-

ble operation. The switching power stage requires par-

ticular attention. Follow these guidelines for good PCB

layout:

1) Place decoupling capacitors as close to the IC as

possible. Keep power ground plane (connected to

PGND) and signal ground plane (connected to

GND) separate.

2) Connect input and output capacitors to the power

ground plane; connect all other capacitors to the

signal ground plane.

3) Keep the high-current paths as short and wide as

possible. Keep the path of switching current (C1 to IN

and C1 to PGND) short. Avoid vias in the switching

paths.

4) If possible, connect IN, LX, and PGND separately to

a large copper area to help cool the IC to further

improve efficiency and long-term reliability.

5) Ensure all feedback connections are short and

direct. Place the feedback resistors as close to the

IC as possible.

6) Route high-speed switching nodes away from sensi-

tive analog areas (FB, COMP).

Thermal Considerations

The MAX1951 uses a fused-lead 8-pin SO package with

a RTHJC rating of 32°C/W. The MAX1951 EV kit layout is

optimized for 1.5A. The typical application circuit shown

in Figure 2c was tested with the existing MAX1951 EV kit

layout at +85°C ambient temperature, and GND lead

temperature was measured at +113°C for a typical

device. The estimated junction temperature was

+138°C. Thermal performance can be further improved

with one of the following options:

1) Increase the copper areas connected to GND, LX,

and IN.

2) Provide thermal vias next to GND and IN, to the

ground plane and power plane on the back side of

PCB, with openings in the solder mask next to the

vias to provide better thermal conduction.

3) Provide forced-air cooling to further reduce case

temperature.

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