MAX3622 データシートの表示（PDF） - Maxim Integrated
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MAX3622 Datasheet PDF : 9 Pages
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Low-Jitter, Precision Clock Generator
with Two Outputs
27pF
25MHz
CRYSTAL
(CL = 18pF)
33pF
X_IN
X_OUT
Figure 4. Crystal, Capacitors Connection
+3.3V
Interfacing with LVPECL Outputs
The equivalent LVPECL output circuit is given in Figure
7. This output is designed to drive a pair of 50Ω trans-
mission lines terminated with 50Ω to VTT = VCC - 2V. If
a separate termination voltage (VTT) is not available,
other termination methods can be used such as shown
in Figures 5 and 6. Unused outputs should be disabled
and may be left open. For more information on LVPECL
terminations and how to interface with other logic fami-
lies, refer to Maxim Application Note HFAN-01.0:
Introduction to LVDS, PECL, and CML.
Interface Models
Figure 7 and Figure 8 show examples of interface models.
VCC
MAX3622 QB
QB
130Ω
Z0 = 50Ω
Z0 = 50Ω
82Ω
130Ω
HIGH
IMPEDANCE
82Ω
Figure 5. Thevenin Equivalent of Standard PECL Termination
QB
MAX3622
QB
0.1μF
Z0 = 50Ω
0.1μF
100Ω
Z0 = 50Ω
150Ω 150Ω
HIGH
IMPEDANCE
QB
QB
ESD
STRUCTURES
Figure 7. Simplified LVPECL Output Circuit Schematic
VDDO_A
DISABLE
NOTE: AC-COUPLING IS OPTIONAL.
Figure 6. AC-Coupled PECL Termination
10Ω
IN
QA_C
10Ω
ESD
STRUCTURES
GNDO_A
Figure 8. Simplified LVCMOS Output Circuit Schematic
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