MAX3674 データシートの表示（PDF） - Maxim Integrated
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MAX3674 Datasheet PDF : 19 Pages
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High-Performance, Dual-Output, Network Clock
Synthesizer
Lock Indicator
The PFD within the PLL generates the lock indicator
and operates by comparing the divided down VCO out-
put (fVCO / M) to a divided down reference clock (fREF /
P). The LOCK output pin indicates that the PLL is
locked (LOCK = 1) when the VCO has obtained phase
and frequency lock with the reference clock. See the
LOCK Detect section in the Applications Information
section for further details.
Internal Register Definitions
The MAX3674 has four 8-bit-wide internal registers for
accessing through the I2C interface. The registers
include two configuration registers (PLL_L and PLL_H),
a command register (CMD), and an ID register (ID).
Tables 1 and 2 show the register map, definitions, and
default values.
Table 1. Register Map
ADDRESS
0x00h
0x01h
0xF0h
0x08h
NAME
PLL_L
PLL_H
CMD
ID
CONTENT
Least significant 8 bits of PLL feedback divider M, M[7:0]
Most significant 2 bits of M, M[9:8] and NA[2:0], NB, P, LOCK
Command register
Unique bit pattern for identification (8’b01010100)
ACCESS
R/W
R/W
W
R
Table 2. Register Definition and Default Values
REGISTER
PLL_L
PLL_H
CMD
ID
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
M7
M6
M5
M4
M3
M2
M1
M0
1
1
1
1
0
1
0
0
M9
M8
NA2
NA1
NA0
NB
P
LOCK
0
1
0
1
0
0
1
x
Command INC (0x01), increase internal PLL frequency M := M + 1
x
x
x
x
0
0
0
1
Command DEC (0x02), decrease internal PLL frequency M := M - 1
x
x
x
x
0
0
1
0
Command LOAD (0x04), update PLL divider configuration, PLL divider M, NA, NB, P := PLL_L, PLL_H
x
x
x
x
0
1
0
0
Command GET (0x08), update the configuration registers, PLL_L, PLL_H := PLL divider M, NA, NB, P
x
x
x
x
1
0
0
0
MAX3674 unique device ID
0
1
0
1
0
1
0
0
10 ______________________________________________________________________________________
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