MAX3674 データシートの表示（PDF） - Maxim Integrated

部品番号

コンポーネント説明

メーカー

MAX3674

High-Performance, Dual-Output, Network Clock Synthesizer

Maxim Integrated 

High-Performance, Dual-Output, Network Clock

Synthesizer

Function Table

PIN

INPUT PINS

REF_SEL

P

M[9:0]

NA[2:0]

NB

PLOAD

ADR[1:0]

SDA, SCL

DEFAULT

(Note 1)

FUNCTION WHEN SET LOW

0

FUNCTION WHEN SET HIGH

1

1

1

01 1111 0100 b

(Note 2)

010

0

0

00

—

Selects REF_CLK input as PLL reference Selects XTAL interface as PLL reference

clock.

clock.

PLL predivider parallel programming interface. See Table 4.

PLL feedback-divider (10-bit) parallel programming interface. See Table 5.

PLL postdivider parallel programming interface. See Table 6.

PLL postdivider parallel programming interface. See Table 7.

Selects the parallel programming

interface. The internal PLL divider

settings (M, NA, NB, and P) are equal to

the setting of the hardware pins. Leaving

the M, NA, NB, and P pins open (floating)

results in a default PLL configuration with

fOUT = 250MHz. PLL settings can be read

through the I2C interface.

Selects the serial (I2C) programming

interface. The internal PLL divider

settings (M, NA, NB, and P) are set and

read through the serial interface.

Address bit = 0

Address bit = 1

See the Programming Through Serial I2C Interface section.

BYPASS

PLL function bypassed.

1

fQA = fREF / NA and

fQB = fREF / (NA
NB)

LOCK = test output

PLL function enabled.

fQA = (fREF / P)
M / NA and

fQB = (fREF / P)
M / (NA
NB)

TEST_EN

0

Normal operation mode. Factory test

Factory test mode enabled.

mode disabled.

CLK_STOPx

1

Output Qx is synchronously disabled in Output Qx is synchronously enabled.

logic-low state.

The device is reset. The output frequency

is zero and the outputs are

asynchronously forced to a logic-low

MR

—

state. After releasing reset (upon the

rising edge of MR and independent on the

state of PLOAD), the MAX3674 reads the

The PLL attempts to lock to the reference

signal. The tLOCK specification applies.

parallel interface (M, NA, NB, and P) to

acquire a valid startup frequency

configuration.

OUTPUT PIN

LOCK

—

PLL is not locked.

PLL is frequency locked.

Note 1: Default states are set by internal input 75kΩ pullup or pulldown resistors.

Note 2: If fREF = 16MHz, the default configuration results in a 250MHz output frequency.

8 _______________________________________________________________________________________

Share Link: