MAX3671 データシートの表示（PDF） - Maxim Integrated

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MAX3671

Low-Jitter Frequency Synthesizer with Selectable Input Reference

Maxim Integrated 

Low-Jitter Frequency Synthesizer

with Selectable Input Reference

PIN

1

2

3

4

5

6

7, 22, 30, 41,

49, 52

8, 14, 23, 29,

42, 48, 53

9

10

11

12

13

15

16

17

18

19

20

21

24

25

26

27

28

31

32

33

34

35

36

NAME

IN0FAIL

RSVD1

RSVD2

REFCLK0

REFCLK0

DM

VCC

GND

MR

REFCLK1

REFCLK1

SEL_CLK

VCC_VCO

CPLL

CREG

FB_SEL

FB_IN

FB_IN

OUTB0

OUTB0

OUTB1

OUTB1

OUTB2

OUTB2

DB

OUTB3

OUTB3

OUTB4

OUTB4

OUTB_EN

OUTA_EN

Pin Description

FUNCTION

REFCLK0 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK0 fails the clock

qualification. Once a failed clock is detected, the indicator status is latched and updated

every 128 PFD cycles (~ 2μs).

Reserved. Leave pin open.

Reserved. Connect to GND.

Reference Clock Input 0, Differential LVPECL

Four-Level Control Input for Reference Clock Input Divider. See Table 1.

Power Supply. Connect to +3.3V.

Supply Ground

Master Reset, LVCMOS/LVTTL Input. Connect this pin high or leave open for normal

operation. Has internal 90k
pullup to VCC. Connect low to reset the device. A reset is not

required at power-up. If the output divider settings are changed on the fly, a reset is

required to phase align the outputs. This input has a 100ns minimum pulse width and is

asynchronous to the reference clock. While in reset, all clock outputs are held to logic-

low. See Table 6.

Reference Clock Input 1, Differential LVPECL

Reference Clock Select, LVCMOS/LVTTL Input. Connect low or leave open to select REFCLK0

as the reference clock. Has internal 90k
pulldown to GND. Connect high to select REFCLK1

as the reference clock.

Power Supply for VCO. Connect to +3.3V.

Connection for PLL Filter Capacitor. Connect a 0.1μF capacitor between this pin and GND.

Connection for VCO Regulator Capacitor. Connect a 0.22μF capacitor between this pin and

GND.

External Feedback Select, LVCMOS/LVTTL Input. Connect high to select external feedback

for zero-delay buffer configuration. Connect low or leave open for internal feedback. Has

internal 90k
pulldown to GND.

External Feedback Clock Input, Differential LVPECL. Used for zero-delay buffer

configuration.

Clock Output B0, Differential LVPECL

Clock Output B1, Differential LVPECL

Clock Output B2, Differential LVPECL

Four-Level Control Input for B-Group Output Divider. See Table 3.

Clock Output B3, Differential LVPECL

Clock Output B4, Differential LVPECL

Three-Level Control Input for B-Group Output Enable. See Table 5.

Three-Level Control Input for A-Group Output Enable. See Table 4.

8 _______________________________________________________________________________________

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