MAX3673 データシートの表示（PDF） - Maxim Integrated

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MAX3673

Low-Jitter Frequency Synthesizer with Selectable Input Reference

Maxim Integrated 

Low-Jitter Frequency Synthesizer

with Selectable Input Reference

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless

otherwise noted.)

PARAMETER

Master Reset (MR) Minimum

Pulse Width

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

100

ns

Propagation Delay from Input to

FB_IN

FB_SEL = 1 (Notes 8, 11)

-120

+120

ps

Propagation Delay from Input to

Any Output

PLL_BYPASS = 1

1.0

ns

Note 1: During the power-on-reset time, the LVPECL outputs are held to logic-low (OUTxx = low, OUTxx = high). See the Power-

On-Reset (POR) section for more information.

Note 2: LVPECL inputs can be AC- or DC-coupled.

Note 3: For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with

VCC pins connected to GND. See Figure 1.

Note 4: Measured with LVPECL input (VIH, VIL) as specified.

Note 5: Measured using reference clock input with 550ps rise/fall time (20% to 80%).

Note 6: When input differential swing is below the specified threshold, a clock failure is declared. See Figure 4.

Note 7: LVPECL outputs terminated 50Ω to VTT = VCC - 2V.

Note 8: Guaranteed by design and characterization.

Note 9: Measured with 50% duty cycle at reference clock input.

Note 10: Measured with 50mVP-P sinusoidal noise on the power supply, fNOISE = 100kHz.

Note 11: Measured with fREFCLKx = fFB_IN and matched slew rates.

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