MAX3624A データシートの表示（PDF） - Maxim Integrated

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MAX3624A

Low-Jitter, Precision Clock Generator with Four Outputs

Maxim Integrated 

Low-Jitter, Precision Clock Generator

with Four Outputs

Interfacing with LVPECL Outputs

The equivalent LVPECL output circuit is given in Figure

8. These outputs are designed to drive a pair of 50Ω

transmission lines terminated with 50Ω to VTT = VCC -

2V. If a separate termination voltage (VTT) is not avail-

able, other termination methods can be used such as

shown in Figure 5 and Figure 6. Unused outputs should

be disabled and may be left open. For more information

on LVPECL terminations and how to interface with other

logic families, refer to Application Note 291: HFAN-

01.0: Introduction to LVDS, PECL, and CML.

+3.3V

Interface Models

Figure 7, Figure 8, and Figure 9 show examples of

interface models.

VCC

VB = 1.4V

VCC

VB

REF_IN

14.5kΩ

VB

MAX3624A Qx

Qx

130Ω

Z0 = 50Ω

Z0 = 50Ω

82Ω

130Ω

HIGH

IMPEDANCE

82Ω

Figure 5. Thevenin Equivalent of Standard PECL Termination

ESD

STRUCTURES

Figure 7. Simplified REF_IN Pin Circuit Schematic

VCC

Qx

MAX3624A

Qx

0.1μF

Z0 = 50Ω

0.1μF

100Ω

Z0 = 50Ω

150Ω 150Ω

HIGH

IMPEDANCE

NOTE: AC-COUPLING IS OPTIONAL.

Figure 6. AC-Coupled PECL Termination

Qx

Qx

ESD

STRUCTURES

Figure 8. Simplified LVPECL Output Circuit Schematic

10 ______________________________________________________________________________________

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