Figure 3: Test and Application Circuit (Stereo Configuration)
TDA7269
+VS
R2
C3
MUTE/
ST-BY 5
C4
C5
+VS
3
R1
IN (L) 7
+
4 OUT (L)
SW1
C1
-
DZ
R5
R7
) R4
R3
t(s SW2
GND 9
duc C2
ro IN (R) 11
lete P duct(s) D94AU087
8 IN- (L)
C8
R6
10 IN- (R)
R9
R8
-
2 OUT (R)
+
R10
1
6
-VS
C9
C7
C6
RL (L)
RL (R)
) - Obsolete Pro APPLICATIONS SUGGESTION
t(s o (Demo Board Schematic)
c bs The recommended values of the external compo-
nents are those shown are the demo board sche-
matic different values can be used: the following
table can help the designer.
u O COMPONENTS
Prod t(s) - R1
R2
lete uc R3
d R4
so ro R5, R8
b P R6, R9
O te R7, R10
le C1, C2
soC3
ObC4, C6
RECOMMENDED
VALUE
10KΩ
15KΩ
18KΩ
15KΩ
18KΩ
560Ω
4.7Ω
1µF
1µF
1000µF
PURPOSE
Mute Circuit
Mute Circuit
Mute Circuit
Mute Circuit
Closed Loop Gain
Setting (*)
Frequency Stability
Input DC
Decoupling
St-By/Mute Time
Constant
Supply Voltage
Bypass
LARGER THAN
RECOMMENDED VALUE
Increase of Dz
Biasing Current
Vpin # 5 Shifted Downward
Vpin # 5 Shifted Upward
Vpin # 5 Shifted Upward
Increase of Gain
Decrease of Gain
Danger of Oscillations
SMALLER THAN
RECOMMENDED VALUE
Vpin # 5 Shifted Upward
Vpin # 5 Shifted Downward
Vpin # 5 Shifted Downward
Danger of Oscillations
Higher Low Frequency
Cutoff
Larger On/Off Time
Smaller On/Off Time
Danger of Oscillations
C5, C7
0.1µF
Supply Voltage
Bypass
Danger of Oscillations
C8, C9
0.1µF
Frequency Stability
Dz
5.1V
Mute Circuit
(*) Closed loop gain has to be => 25dB
5/7