MAX4524LETB(2007) データシートの表示（PDF） - Maxim Integrated

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MAX4524LETB
(Rev.:2007)

Low-Voltage, Single-Supply Analog Multiplexers/Switches

Maxim Integrated 

Low-Voltage, Single-Supply Analog

Multiplexers/Switches

Detailed Description

The MAX4524L/MAX4525L are low-voltage, single-sup-

ply CMOS analog switches that operate from a single

supply of +2V to +12V. Operation with a +12V supply

optimizes the performance by reducing their on-resis-

tance to 100Ω. The MAX4524L is configured as a 4-

channel multiplexer/demultiplexer and the MAX4525L is

a double-pole/double-throw (DPDT) switch. These

devices have an inhibit input (INH) to simultaneously

open all signal paths. Each switch can handle rail-to-

rail analog signals. The off-leakage current is typically

only 0.1nA at +25°C and 10nA (max) over temperature.

All digital inputs have 0.8V to 2.0V logic-level thresh-

olds, ensuring TTL/CMOS-logic compatibility when

using a single +12V supply.

Applications Information

Power-Supply Considerations

The MAX4524L/MAX4525Ls’ construction is typical of

most CMOS analog switches. The supply input, V+, is

used to power the internal CMOS switches and set the

limits of the analog voltage on any switch. Reverse ESD

protection diodes are internally connected between

each analog signal pin and both V+ and GND. If any

analog signal exceeds V+ or goes below GND, one of

these diodes conducts. During normal operation, these

reverse-biased ESD diodes leak, forming the only cur-

rent drawn from V+ or GND. Virtually all the analog

leakage current comes from the ESD diodes. Although

the ESD diodes on a given signal pin are identical, and

therefore fairly well balanced, they are reverse biased

differently. Each is biased by either V+ or GND and the

analog signal. This means that leakage varies as the

signal varies. The difference in the two diode leakages

to the V+ and GND pins constitutes the analog signal-

path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not

to the other switch terminal. This is why both sides of a

given switch can show leakage currents of either the

same or opposite polarity.

There is no connection between the analog signal

paths and GND. V+ and GND power the internal logic

and logic-level translators, and set both the input and

output logic limits. The logic-level translators convert

the logic levels into switched V+ and GND signals to

drive the gates of the analog signals. This drive signal

is the only connection between the logic supplies (and

signals) and the analog supplies.

Test Circuits/Timing Diagrams

V+

V+

ADDA

NO0

V+

ADDB

NO1–NO3

MAX4524L

VINH

INH

COM

GND

50Ω

300Ω

VOUT

35pF

V+

VINH

50%

0V

VNO0

VOUT

90%

0V

tON

90%

tOFF

V+

V+

ADD

NO_

V+

NC_

MAX4525L

VINH

INH

COM_

GND

50Ω

300Ω

VOUT

35pF

V+

VINH

50%

0V

VNO_

VOUT

90%

0V

tON

90%

tOFF

Figure 1. Inhibit Switching Times

6 _______________________________________________________________________________________

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