MAX4948EBA(2007) データシートの表示（PDF） - Maxim Integrated
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MAX4948EBA Datasheet PDF : 13 Pages
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Hex SPDT Data Switch
Detailed Description
The MAX4947 triple DPDT and the MAX4948 hex SPDT
analog switches operate from a single +1.8V to
+5.5V supply. These devices are fully specified for +3V
applications.
The MAX4947/MAX4948 have a guaranteed 4Ω (typ) on-
resistance and a low 30pF (typ) capacitance that makes
the switch ideal for data switching applications. The
MAX4947 has three logic inputs to control two switches in
pairs and the MAX4948 has one logic control input and
an enable input (EN) to disable the switches.
Applications Information
Digital Control Inputs
The MAX4947/MAX4948 provide a digital control logic
input, CB_. CB_ controls the position of the switches as
shown in the Pin Configurations/Truth Tables. Driving
CB_ rail-to-rail minimizes power consumption.
The MAX4948 features an EN input to turn all switches
on or off. When EN is driven high, CB is disabled, and
the analog inputs enter a high-impedance state. Drive
EN low to turn the switches on and enable CB.
Analog Signal Levels
The on-resistance of the MAX4947/MAX4948 is very low
and stable as the analog input signals are swept
from ground to VCC (see the Typical Operating
Characteristics). These switches are bidirectional, allow-
ing NO_, NC_, and COM_ to be configured as either
inputs or outputs.
Power-Supply Biasing
Power-supply bypassing improves noise margin and
prevents switching noise to propagate from VCC supply
to other components. A 0.1µF capacitor connected
from V+ to GND is adequate for most applications.
Power-Supply Sequencing
CMOS devices require proper power-supply sequencing.
Always apply VCC before the analog signals, especially
if the input signal is not current limited.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout, and recommend-
ed reflow temperature profile, as well as the latest infor-
mation on reliability testing results, go to the Maxim
website at www.maxim-ic.com/ucsp for the Application
Note: UCSP-A Wafer-Level Chip-Scale Package.
Timing Circuits/Timing Diagrams
MAX4947/
MAX4948
VN_
NO_
OR NC_
LOGIC
INPUT
CB_
GND
VCC
VCC
COM_
RL
VOUT
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VN_
RL
RL + RON
Figure 1. Switching Time
LOGIC VCC
INPUT 0V
50%
tr < 5ns
tf < 5ns
50%
SWITCH 0V
OUTPUT
tOFF
VOUT 0.9 x V0UT
0.9 x VOUT
tON
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
8 _______________________________________________________________________________________
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