MAX4948(2007) データシートの表示（PDF） - Maxim Integrated
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MAX4948 Datasheet PDF : 13 Pages
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Hex SPDT Data Switch
Timing Circuits/Timing Diagrams (continued)
MAX4947/
MAX4948
VN_
LOGIC
INPUT
VCC
VCC
NC_
COM_
NO_
CB_
GND
VOUT
RL
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make-Interval
LOGIC VCC
INPUT
50%
0V
VOUT
0.9 x VOUT
tBBM
TxD+
A+
B+
INPUT A+
Rs
•
CL
INPUT A-
•
•
•
•
•
TxD-
•
A-
B-
OUTPUT B+
Rs
Rs = 39Ω
CL = 50pF
CL
OUTPUT B-
tri
90%
50%
10%
tskew_i
90%
50%
10%
tfi
tro
90%
50%
10%
tskew_o
90%
50%
10%
tfo
|tro - tri| DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
|tfo - tfi| DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
|tskew_o| CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
|tskew_i| CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
Figure 3. Input/Output Skew Timing Diagram
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