MAX519ACSE データシートの表示（PDF） - Maxim Integrated
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MAX519ACSE Datasheet PDF : 16 Pages
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2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Digital-Analog Glitch Impulse
Signal to Noise + Distortion
Ratio (MAX517, MAX519)
SINAD
Code 128 to 127
VREF_ = 4Vp-p at 1kHz, VDD = 5V,
Code = FF hex
12
nV-s
87
dB
Multiplying Bandwidth
(MAX517, MAX519)
VREF_ = 4Vp-p, 3dB bandwidth
1
MHz
Wideband Amplifier Noise
POWER REQUIREMENTS
60
µVRMS
Supply Voltage
Supply Current
VDD
4.5
MAX517C
1.5
Normal mode, output(s)
MAX517E/M
1.5
unloaded, all digital inputs
IDD
at 0V or VDD
MAX518C, MAX519C
2.5
MAX518E/M, MAX519E/M
2.5
5.5 V
3.0
3.5
mA
5
6
Power-down mode
4
20 µA
TIMING CHARACTERISTICS
(VDD = 5V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Serial Clock Frequency
fSCL
Bus Free Time Between a STOP and a
START Condition
tBUF
0
400
kHz
1.3
µs
Hold Time, (Repeated) Start Condition
tHD, STA
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
High Period of the SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated START Condition
tSU, STA
0.6
µs
Data Hold Time
tHD, DAT (Note 9)
0
0.9
µs
Data Setup Time
tSU, DAT
100
ns
Rise Time of Both SDA and SCL Signals, Receiving
tR
(Note 10)
20 + 0.1Cb
300
ns
Fall Time of Both SDA and SCL Signals, Receiving
tF
(Note 10)
20 + 0.1Cb
300
ns
Fall Time of SDA Transmitting (Note 7)
tF
ISINK ≤ 6mA (Note 10) 20 + 0.1Cb
250
ns
Setup Time for STOP Condition
tSU, STO
0.6
µs
Capacitive Load for Each Bus Line
Cb
400
pF
Pulse Width of Spike Suppressed
tSP
(Notes 6, 11)
0
50
ns
Note 1: For the MAX518 (full-scale = VDD) the last three codes are excluded from the TUE and DNL specifications, due to the limited
output swing when loaded with 10kΩ to GND.
Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.
Note 4: VREF_ = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 5: VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex.
Note 6: Guaranteed by design.
Note 7: I2C compatible mode.
Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 10: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD.
Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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