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MAX5201ACUB データシートの表示(PDF) - Maxim Integrated

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MAX5201ACUB Datasheet PDF : 13 Pages
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Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in µMAX
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ...............................................-0.3V to +6V
AGND to DGND.........................................……….-0.3V to +0.3V
REF, OUT to AGND.................................…-0.3V to (VDD + 0.3V)
CLR, LDAC, SCLK, DIN, CS to DGND .......-0.3V to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) ........444.4mW
Operating Temperature Ranges
MAX520_CUB .....................................................0°C to +70°C
MAX520_EUB ........................................…….-40°C to +105°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5200/MAX5201
(VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), output load = 10kin parallel with 250pF, TA = TMIN to TMAX, unless other-
wise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
STATIC PERFORMANCE (Note 1)
Resolution
N
16
Bits
Integral Nonlinearity (Note 2)
MAX520_AEUB
INL MAX520_ACUB
±10 ±20
±10
±20
LSB
Differential Nonlinearity
(Note 2)
DNL
MAX520_BEUB
MAX520_A_UB (Note 3)
MAX520_BEUB (0°C to +105°C) (Note 3)
MAX520_BEUB (-40°C to 0°C)
±20 ±40
±1
±1
LSB
±2
Offset Error
Inferred from measurement at 1C00 hex
and FFFF hex
±3
±25
mV
Gain Error
GE
Within DAC output range (Note 4)
±0.01 ±1 %FSR
Power-Supply Rejection
DYNAMIC PERFORMANCE
PSR VDD = 5V ±5%, midscale input
±0.06 ±0.5 mV/V
DAC Output Range
Output-Voltage Slew Rate
(Note 2)
SR
0 to
VDD
V
0.6
V/µs
Output Settling Time
Output Noise
To ±1LSB of FS,
VSTEP = 0.25 × VREF to 0.75 × VREF
DAC code = 8400 hex, 10kHz
25
µs
175
nV/Hz
DAC Glitch Impulse
Major carry transition (code 7FFF hex to
code 8000 hex)
10
nVs
Digital Feedthrough
Code = 0000 hex; CS = VDD;
LDAC = 0; SCLK, DIN = 0 or VDD
10
nVs
Wake-Up Time
From software shutdown to 90% of output
50
µs
code = FFFF hex, CREF = 0.1µF
Power-Up Time
From power applied to 90% of output
code = FFFF hex
10
ms
2 _______________________________________________________________________________________

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