MAX5134 データシートの表示（PDF） - Maxim Integrated
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MAX5134 Datasheet PDF : 19 Pages
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Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD ≥ VDVDD, VGND = 0, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS (Note 7)
Analog Supply Voltage Range
AVDD
Digital Supply Voltage Range
DVDD
2.7
5.25
V
2.7
AVDD
V
Supply Current
(MAX5134/MAX5135)
IAVDD
IDVDD
No load, all digital inputs at 0 or DVDD
2.5
3.6
mA
1
10
µA
Supply Current
(MAX5136/MAX5137)
IAVDD
IDVDD
No load, all digital inputs at 0 or DVDD
1.5
2.3
mA
1
10
µA
Power-Down Supply Current
IAVPD
IDVPD
No load, all digital inputs at 0 or DVDD
0.2
2
µA
0.1
2
TIMING CHARACTERISTICS (Note 8) (Figure 1)
Serial-Clock Frequency
fSCLK
0
30
MHz
SCLK Pulse-Width High
tCH
13
ns
SCLK Pulse-Width Low
tCL
13
ns
CS Fall-to-SCLK Fall Setup Time
tCSS
8
ns
SCLK Fall-to CS-Rise Hold Time
tCSH
5
ns
DIN-to-SCLK Fall Setup Time
tDS
10
ns
DIN-to-SCLK Fall Hold Time
tDH
2
ns
SCLK Fall to READY Transition
tSRL
(Note 9)
30
ns
CS Pulse-Width High
tCSW
33
ns
LDAC Pulse Width
tLDACPWL
33
ns
Note 1: Static accuracy tested without load.
Note 2: Linearity is tested within 20mV of GND and AVDD, allowing for gain and offset error.
Note 3: Codes above 2047 are guaranteed to be within ±8 LSB.
Note 4: Gain and offset tested within 100mV of GND and AVDD.
Note 5: Guaranteed by design.
Note 6: Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < DVDD - 0.6V
or VI > 0.5V. At VI = 2.2V with DVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input level com-
patible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing.
Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without
AVDD.
Note 8: All timing specifications are with respect to the digital input and output thresholds.
Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
CS
tCSS
tCL tCH
COMMAND EXECUTED ON
24TH FALLING EDGE OF SCLK
tCSW
tCSH
SCLK
tDS tDH
DIN X
C7
C6
C5
D3
D2
D1
D0
X
tSRL
READY
X = DON'T CARE.
Figure 1. Serial-Interface Timing Diagram
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