MAX531BESD データシートの表示（PDF） - Maxim Integrated

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MAX531BESD

+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs

Maxim Integrated 

+5V, Low-Power, Voltage-Output

Serial 12-Bit DACs

____________________Pin Description

PIN

MAX531

MAX538

MAX539

1

—

2

1

3

—

4

2

5

3

6

4

7

—

8

5

9

6

10

—

11

—

12

7

13

8

14

—

NAME

BIPOFF

DIN

CLR

SCLK

CS

DOUT

DGND

AGND

REFIN

REFOUT

VSS

VOUT

VDD

RFB

FUNCTION

Bipolar Offset/Gain

Resistor

Serial Data Input

Clear. Asynchronously sets

DAC register to 000 hex.

Serial Clock Input

Chip Select, active low

Serial Data Output for

daisy-chaining

Digital Ground

Analog Ground

Reference Input

Reference Output,

2.048V

Negative Power Supply

DAC Output

Positive Power Supply

Feedback Resistor

_______________Detailed Description

General DAC Discussion

The MAX531/MAX538/MAX539 use an “inverted” R-2R

ladder network with a single-supply CMOS op amp to con-

vert 12-bit digital data to analog voltage levels (see

Functional Diagram). The term “inverted” describes the

ladder network because the REFIN pin in current-output

DACs is the summing junction, or virtual ground, of an op

amp. However, such use would result in the output voltage

being the inverse of the reference voltage. The

MAX531/MAX538/MAX539’s topology makes the output

the same polarity as the reference input.

An internal reset circuit forces the DAC register to reset to

000 hex on power-up. Additionally, a clear CLR pin, when

held low, sets the DAC register to 000 hex. CLR operates

asynchronously and independently from the chip-select

(CS) pin.

Buffer Amplifier

The output buffer is a unity-gain stable, rail-to-rail output,

BiCMOS op amp. Input offset voltage and CMRR are

trimmed to achieve better than 12-bit performance.

Settling time is 25µs to 0.01% of final value. The settling

time is considerably longer when the DAC code is initially

set to 000 hex, because at this code the op amp is com-

pletely debiased. Start from code 001 hex if necessary.

The output is short-circuit protected and can drive a 2kΩ

load with more than 100pF load capacitance.

CS

tCSH0

SCLK

tDS

DIN

DOUT

tCSS

tCH

tCL

tDH

tDO

tCSW

tCSH1

tCS1

Figure 1. Timing Diagram

8 _______________________________________________________________________________________

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