MAX536(2011) データシートの表示（PDF） - Maxim Integrated

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MAX536
(Rev.:2011)

Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Maxim Integrated 

Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

;; ; CS

SCK

1

8

9

SDI

D15 D14 D13..........

MSB

SDO

Q15..........

MSB FROM

PREVIOUS WRITE

;;16

..........D2 D1 D0

COMMAND

EXECUTED

LSB

...........Q0

LSB FROM

PREVIOUS WRITE

Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or VDD)

;CS

SCK

1

SDI

;;;; 8

9

INPUT REGISTER(S)

UPDATED

16

D15 D14 D13..........

..........D2 D1 D0

MSB

LSB

SDO

LDAC

Q15..........

MSB FROM

PREVIOUS WRITE

..........Q0

LSB FROM

PREVIOUS WRITE

DACs

UPDATED

Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC

CS

tCSO

tCSS

SCK

tDS tDH

SDI

tDV

SDO

tCH

tCL

tCSW

tCP

tCSH

tCSI

tDO1 tDO2

tTR

LDAC*

*USE OF LDAC IS OPTIONAL

tLDAC

Figure 6. Detailed Serial-Interface Timing Diagram

14 ______________________________________________________________________________________

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