MAX536(2011) データシートの表示（PDF） - Maxim Integrated

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MAX536
(Rev.:2011)

Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Maxim Integrated 

Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

SS is an input intended for use in a multimaster environ-

ment. However, SS or unused PORT D bit RXD, TXD, or

possibly MISO (if DAC readback is not used) should be

configured as a general-purpose output and used as CS by

setting the appropriate Data Direction Register bit.

Unipolar Output

For a unipolar output, the output voltages and the reference

inputs are the same polarity. Figure 10 shows the

MAX536/MAX537 unipolar output circuit, which is also the typ-

ical operating circuit. Table 5 lists the unipolar output codes.

The SPCR configuration (memory location $1028) is shown

below:

BIT

76 5

4

3

2

1

0

NAME

SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0

SETTING AFTER RESET

00 0

0

0 1 U* U*

Bipolar Output

The MAX536/MAX537 outputs can be configured for

bipolar operation using Figure 11’s circuit. One op amp

and two resistors are required per DAC. With R1 = R2:

VOUT = VREF [(2NB/4096) - 1]

where NB is the numeric value of the DAC’s binary input

code. Table 6 shows digital codes and corresponding

output voltages for Figure 11’s circuit.

SETTING FOR TYPICAL SPI COMMUNICATION

01 0

1

0

0 0** 1**

*U = Unknown

**Depends on µP clock frequency.

Always configure the 68HC11 as the “master” controller

and the MAX536/MAX537 as the “slave” device.

When MSTR = 1 in the SPCR, a write to the Serial

Peripheral Data I/O Register (SPDR), located at memory

location $102A, initiates the transmission/reception of

data. The data transfer is monitored and the appropri-

ate flags are set in the Serial Peripheral Status

Register (SPSR).

The SPSR configuration is shown below:

BIT

7

6

5

4

32

1

0

NAME

SPIF WCOL – MODF –

–

–

–

RESET CONDITIONS

0

0

0

0

00

0

0

An example of 68HC11 programming code for a

two-byte SPI transfer to the MAX536/MAX537 is given in

Table 4. SS is used for CS, the high byte of MAX536/

MAX537 digital data is stored in memory location $0100,

and the low byte is stored in memory location $0101.

Table 5. Unipolar Code Table

DAC CONTENTS

MSB

LSB

1111 1111 1111

ANALOG OUTPUT

+VREF

(

—4—09—5

4096

)

1000 0000 0001

+VREF

(

—2—04—9

4096

)

1000 0000 0000

+VREF ( —2—04—8 ) = —+—VR—E—F

4096

2

0111 1111 1111

+VREF

(

—2—04—7

4096

)

0000

0000

0000 0001

0000 0000

+VREF

(

——1 —

4096

)

0V

Table 6. Bipolar Code Table

DAC CONTENTS

MSB

LSB

1111 1111 1111

ANALOG OUTPUT

+VREF ( —22—0044—87 )

1000 0000 0001

+VREF ( —2—014—8 )

Interfacing to Other Controllers

When using MICROWIRE, refer to the section on Inter-

facing to the M68HC11 for guidance, since MICROWIRE

can be considered similar to SPI when CPOL = 0 and

CPHA = 0. When interfacing to Intel’s 80C51/80C31

microcontroller family, use bit-pushing to configure a

desired port as the MAX536/MAX537 interface port. Bit-

pushing involves arbitrarily assigning I/O port bits as

interface control lines, and then writing to the port each

time a signal transition is required.

1000

0111

0000 0000

1111 1111

0000 0000 0001

0000 0000 0000

NOTE:

1

LSB

=

(VREF)

(

1

4096

)

0V

-VREF ( —2—014—8 )

-VREF ( —22—0044—78 )

-VREF

(

—20—4—8

2048

)

=

-VREF

20 ______________________________________________________________________________________

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