MAX536(2011) データシートの表示（PDF） - Maxim Integrated
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MAX536 Datasheet PDF : 24 Pages
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Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset
Pulse Width (Note 2)
tPOR
SCK Clock Period
tCP
SCK Pulse Width High
tCH
SCK Pulse Width Low
tCL
CS Fall to SCK Rise
Setup Time
tCSS
SCK Rise to CS Rise
Hold Time
tCSH
SDI Setup Time
tDS
SDI Hold Time
tDH
SCK Rise to SDO Valid
Propagation Delay (Note 6)
tDO1
1kΩ pullup on SDO
to VDD, CLOAD = 50pF
SDO high
SDO low
SCK Fall to SDO Valid
Propagation Delay (Note 7)
CS Fall to SDO Enable
(Note 8)
tDO2
tDV
1kΩ pullup on SDO
to VDD, CLOAD = 50pF
SDO high
SDO low
MIN TYP MAX
20
100
30
30
20
10
40
26
0
78
105
50
80
81
110
53
85
27
45
CS Rise to SDO Disable
(Note 9)
tTR
40
60
SCK Rise to CS Fall Delay
tCS0 Continuous SCK, SCK edge ignored
20
CS Rise to SCK Rise
Hold Time
tCS1 SCK edge ignored
20
LDAC Pulse Width Low
tLDAC
30
CS Pulse Width High
tCSW
40
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: TUE is specified with no resistive load.
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
Note 5: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0 to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.
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