MAX536A データシートの表示（PDF） - Maxim Integrated

部品番号

コンポーネント説明

メーカー

MAX536A

Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Maxim Integrated 

Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

ELECTRICAL CHARACTERISTICS—MAX537 (continued)

(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless

otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

CS Fall to SDO Enable

tDV

CLOAD = 50pF

MAX537_C/E

MAX537_M

75

140

170

CS Rise to SDO Disable

(Note 10)

tTR

CLOAD = 50pF

MAX537_C/E

MAX537_M

70

130

165

SCK Rise to CS Fall Delay

tCS0

Continuous SCK,

SCK edge ignored

MAX537_C/E

MAX537_M

35

40

CS Rise to SCK Rise

Hold Time

tCS1 SCK edge ignored

MAX537_C/E

MAX537_M

35

40

LDAC Pulse Width High

tLDAC

MAX537_C/E

MAX537_M

50

70

CS Pulse Width High

tCSW

MAX537_C/E

MAX537_M

100

125

UNITS

ns

ns

ns

ns

ns

ns

Note 2: Guaranteed by design.

Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.

Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.

Note 5: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0V to 5V.

Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO

pin has an internal active pull-up.)

Note 7: Serial data clocked out of SDO on SCK’s rising edge.

Note 10: When disabled, SDO is internally pulled high.

_______________________________________________________________________________________ 7

Share Link: