MAX550A データシートの表示（PDF） - Maxim Integrated
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MAX550A
Maxim Integrated
MAX550A Datasheet PDF : 16 Pages
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+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
Table 2. MAX548A Serial-Interface Programming Commands
CONTROL BYTE
DATA BYTE
Loaded First
Loaded Last
UB1 UB2 UB3 C2 C1 C0 A1 A0 D7........D0
UNASSIGNED COMMANDS
X
X
X 00X00
XXXXXXXX
X
X
X 1XX00
XXXXXXXX
COMMANDS LOADING INPUT REGISTER(S) ONLY
LDAC
Pin 6
X
X
COMMAND
(Commands executed on CS’s rising edge)
Unassigned command
Unassigned operation
X
X
X 0 0 X 0 1 8-Bit DAC Data X
Load DAC A input register. DAC B input register
and both DAC registers unchanged.
X
X
X 0 0 X 1 0 8-Bit DAC Data X
Load DAC B input register. DAC A input register
and both DAC registers unchanged.
X
X
X 0 0 X 1 1 8-Bit DAC Data X
Load both DAC input registers. Both DAC regis-
ters unchanged.
COMMANDS UPDATING DAC REGISTER(S)
X
X
X 01000
XXXXXXXX
Update both DAC registers with current contents
X
of their input registers. Both input registers
unchanged.
X
X
X 0 1 0 0 1 8-Bit DAC Data X
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
X
X
X 0 1 0 1 0 8-Bit DAC Data X
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
X
X
X 0 1 0 1 1 8-Bit DAC Data X
Load both DAC input registers and update both
DAC registers.
X
X
X 01100
XXXXXXXX
Update both DAC registers with current contents
0
of their input registers. Both input registers
unchanged.
X
X
X 0 1 1 0 1 8-Bit DAC Data 0
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
X
X
X 0 1 1 1 0 8-Bit DAC Data 0
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
X
X
X 0 1 1 1 1 8-Bit DAC Data 0
Load both DAC input registers and update both
DAC registers.
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X 01100
XXXXXXXX
1
After CS’s rising edge and on LDAC’s falling
edge, update both DAC registers with current
contents of their input registers. Both input regis-
ters unchanged.
Load DAC A input register. After CS’s rising edge
X
X
X 0 1 1 0 1 8-Bit DAC Data 1
and on LDAC’s falling edge, update both DAC
registers.
Load DAC B input register. After CS’s rising edge
X
X
X 0 1 1 1 0 8-Bit DAC Data 1
and on LDAC’s falling edge, update both DAC
registers.
Load both DAC input registers. After CS’s rising
X
X
X 0 1 1 1 1 8-Bit DAC Data 1
edge and on LDAC’s falling edge, update both
DAC registers.
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