MAX5942BCSE データシートの表示（PDF） - Maxim Integrated

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MAX5942BCSE

IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices

Maxim Integrated 

IEEE 802.3af Power-Over-Ethernet

Interface/PWM Controller for Power Devices

Pin Description

PIN

NAME

FUNCTION

1

V+

High-Voltage Startup Input. Referenced to V-. Connect directly to an input voltage range between 18V to 67V.

Connects internally to a high-voltage linear regulator that generates VCC during startup.

Line Regulator Input. Referenced to V-. VDD is the input to the linear regulator that generates VCC. For

2

VDD

supply voltages less than 36V, connect VDD and V+ to the supply. For supply voltages greater than 36V,

VDD receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V.

Bypass VDD to V- with a 4.7µF capacitor.

3

FB

Fixed-Gain Inverting Amplifier Input. Referenced to V-. Connect a voltage-divider from the regulated output

to FB. The noninverting input of the amplifier is referenced to +2.4V

Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately

4

SS_SHDN 0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the

capacitor. Disable the PWM controller by pulling SS_SHDN below 0.25V.

Undervoltage Lockout Programming Input for Power Mode. Referenced to VEE. When UVLO is above its

threshold, the device enters the power mode. Connect UVLO to VEE to use the default undervoltage lockout

5

UVLO threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series

resistance value of the external resistors must add to 25.5kΩ (±1%) and replaces the detection resistor. To

keep the device in undervoltage lockout, pull UVLO between VTH,G,UVLO and VREF,UVLO.

6

RCL Classification Setting. Referenced to VEE. Add a resistor from RCL to VEE to set a PD class (see Table 1).

Gate of Internal N-Channel Power MOSFET. Referenced to VEE . GATE sources 10µA when the device

7

GATE

enters the power mode. Connect an external 100V ceramic capacitor from GATE to VOUT to program the

inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection and classification functions

operate normally when GATE is pulled to VEE.

8

VEE

Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect VEE to

- 4 8V .

9

OUT Output Voltage. Referenced to VEE. Drain of the integrated isolation N-channel power MOSFET. Connect

OUT to V-.

Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high

10

PGOOD impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled

to OUT (given that VOUT is at least 5V below GND).

Power-Good Indicator Output, Active Low, Open Drain. PGOOD is referenced to VEE. PGOOD is pulled to

11

PGOOD VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high

impedance.

12

GND Ground. Referenced to VEE. GND is the positive input power.

Current-Sense Input. Referenced to V-. Turns power switch off if VCS rises above 465mV for cycle-by-cycle

13

CS current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller

through a leading-edge blanking circuit.

14

V-

Ground. V- is the ground terminal of the PWM controller.

15

NDRV Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET.

Regulated IC Supply. Referenced to V-. Provides power for MAX5942_. VCC is regulated from VDD during

16

VCC normal operation and from V+ during startup. Bypass VCC with a 10µF tantalum capacitor in parallel with a

0.1µF ceramic capacitor to V-.

10 ______________________________________________________________________________________

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