MAX6303 データシートの表示（PDF） - Maxim Integrated
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MAX6303 Datasheet PDF : 12 Pages
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+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
VCC
WDI
tWD
tRP
0V
VCC
RESET
0V
NORMAL MODE (WDS = GND)
Figure 2a. Watchdog Timing Diagram, WDS = GND
VCC
WDI
tWD x 500
tRP
0V
VCC
RESET
0V
EXTENDED MODE (WDS = VCC)
Figure 2b. Watchdog Timing Diagram, WDS = VCC
watchdog counter. When WDI is left unconnected, the
watchdog timer is cleared by this internal driver just
before the timeout period is reached (the internal driver
pulls WDI high at about 94% of tWD). When WDI is
three-stated, the maximum allowable leakage current of
the device driving WDI is 10µA.
In normal mode (WDS = GND), the watchdog timer
cannot be disabled by three-stating WDI. WDI is a
high-impedance input in this mode. Do not leave WDI
unconnected in normal mode.
Applications Information
Selecting the Reset and Watchdog
Timeout Capacitor
The reset timeout period is adjustable to accommodate
a variety of µP applications. Adjust the reset timeout
period (tRP) by connecting a specific value capacitor
(CSRT) between SRT and ground (Figure 3). Calculate
the reset timeout capacitor as follows:
CSRT = tRP/2.67
VCC
GND
VCC
MAX6301
SRT MAX6302
0.1µF
MAX6303
SWT MAX6304
CSRT
CSWT
CSRT
=
tRP
2.67
CSRT in pF
tRP in µs
CSWT
=
tWD
2.67
CSWT in pF
tWD in µs
Figure 3. Calculating the Reset (CSRT) and Watchdog (CSWT)
Timeout Capacitor Values
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