µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
RESET
tWDI < tWD1 (min)
WDI
WDPO
Figure 2. Fast Fault Timing
RESET
FAST FAULT
tWDI < tWD2 (max)
WDI
WDPO
Figure 3. Slow Fault Timing
SLOW FAULT
RESET
tWD1 (max) < tWDI < tWD2 (min)
WDI
H
WDPO L
Figure 4. Normal Operation, WDPO Not Asserted
NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)
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