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MAX713CSE(2002) データシートの表示(PDF) - Maxim Integrated

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MAX713CSE
(Rev.:2002)
MaximIC
Maxim Integrated MaximIC
MAX713CSE Datasheet PDF : 17 Pages
First Prev 11 12 13 14 15 16 17
NiCd/NiMH Battery
Fast-Charge Controllers
The voltage loop is stabilized by the output filter
capacitor. A large filter capacitor is required only if the
load is going to be supplied by the MAX712/MAX713 in
the absence of a battery. In this case, set COUT as:
COUT (in farads) = (50 x ILOAD) / (VOUT x BWVRL)
where BWVRL = loop bandwidth in Hz
(10,000 recommended)
COUT > 10µF
ILOAD = external load current in amps
VOUT = programmed output voltage
(VLIMIT x number of cells)
Current Loop
Figure 6 shows the current-regulation loop for a linear-
mode circuit. To ensure loop stability, make sure that
the bandwidth of the current regulation loop (BWCRL) is
lower than the pole frequency of transistor Q1 (fB). Set
BWCRL by selecting C2.
BWCRL in Hz = gm / C2, C2 in farads,
gm = 0.0018 Siemens
The pole frequency of the PNP pass transistor, Q1, can
be determined by assuming a single-pole current gain
response. Both fT and Bo should be specified on the
data sheet for the particular transistor used for Q1.
fB in Hz = fT / Bo, fT in Hz, Bo = DC current gain
Condition for Stability of Current-Regulation Loop:
BWCRL < fB
The MAX712/MAX713 dissipate power due to the cur-
rent-voltage product at DRV. Do not allow the power
dissipation to exceed the specifications shown in the
Absolute Maximum Ratings. DRV power dissipation can
be reduced by using the cascode connection shown in
Figure 5 or by using a switch-mode circuit.
Power dissipation due to DRV sink current =
(current into DRV) x (voltage on DRV)
Voltage-Slope Cutoff
The MAX712/MAX713’s internal analog-to-digital con-
verter has 2.5mV of resolution. It determines if the bat-
tery voltage is rising, falling, or unchanging by
comparing the battery’s voltage at two different times.
After power-up, a time interval of tA ranging from 21sec
to 168sec passes (see Table 3 and Figure 8), then a
battery voltage measurement is taken. It takes 5ms to
perform a measurement. After the first measurement is
complete, another tA interval passes, and then a
second measurement is taken. The two measurements
are compared, and a decision whether to terminate
charge is made. If charge is not terminated, another full
two-measurement cycle is repeated until charge is
terminated. Note that each cycle has two tA intervals
and two voltage measurements.
The MAX712 terminates fast charge when a compari-
son shows that the battery voltage is unchanging. The
MAX713 terminates when a conversion shows the bat-
tery voltage has fallen by at least 2.5mV per cell. This is
the only difference between the MAX712 and MAX713.
Temperature Charge Cutoff
Figure 9a shows how the MAX712/MAX713 detect over-
and under-temperature battery conditions using negative
temperature coefficient thermistors. Use the same model
thermistor for T1 and T2 so that both have the same
nominal resistance. The voltage at TEMP is 1V (referred
to BATT-) when the battery is at ambient temperature.
The threshold chosen for THI sets the point at which
fast charging terminates. As soon as the voltage-on
TEMP rises above THI, fast charge ends, and does not
restart after TEMP falls below THI.
The threshold chosen for TLO determines the tem-
perature below which fast charging will be inhibited.
If TLO > TEMP when the MAX712/MAX713 start up, fast
charge will not start until TLO goes below TEMP.
The cold temperature charge inhibition can be disabled
by removing R5, T3, and the 0.022µF capacitor; and by
tying TLO to BATT-.
To disable the entire temperature comparator charge-
cutoff mechanism, remove T1, T2, T3, R3, R4, and R5,
and their associated capacitors, and connect THI to V+
and TLO to BATT-. Also, place a 68kQ resistor from
REF to TEMP, and a 22kresistor from BATT- to TEMP.
Some battery packs come with a temperature-detecting
thermistor connected to the battery pack’s negative
VOLTAGE
RISES
NEGATIVE
ZERO
VOLTAGE
VOLTAGE
SLOPE
SLOPE
CUTOFF FOR MAX712
CUTOFF FOR MAX712 OR MAX713
ZERO
RESIDUAL
NEGATIVE
RESIDUAL
0
POSITIVE RESIDUAL
t
5
5
5
5
5
5
tA ms tA ms tA ms tA ms tA ms tA ms
INTERVAL INTERVAL INTERVAL INTERVAL INTERVAL INTERVAL
NOTE: SLOPE PROPORTIONAL TO VBATT
Figure 8. Voltage Slope Detection
12 ______________________________________________________________________________________

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