MAXQ1850-BNS データシートの表示（PDF） - Maxim Integrated
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MAXQ1850-BNS Datasheet PDF : 3 Pages
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ABRIDGED DATA SHEET
Secure Cryptographic Controller
with Rapid Zeroization Technology
Detailed Features
♦ High-Performance, Low-Power, 32-Bit MAXQ30
RISC Core
♦ Single 3.3V Supply Enables Low Power/Flexible
Interfacing
♦ DC to 16MHz Code Execution Across Entire
Operating Range
♦ Up to 65MHz Cryptography Engine Execution to
Reduce Processing Time
♦ On-Chip 2x/4x Clock Multiplier
♦ 33 Instructions
♦ Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
♦ 16-Bit Instruction Word, 32-Bit Internal Data Bus
♦ 16 x 32-Bit Accumulators
♦ Up to 16 General-Purpose I/O Pins
♦ 5V Tolerant I/O
♦ Virtually Unlimited Software Stack
♦ Optimized for C-Compiler (High-Speed/Density Code)
♦ Memory Features
256KB Flash, Composed of 512 Byte Sectors
(1K Erase/Write Cycles per Sector)
8KB Battery-Backed Data SRAM
Dedicated Cryptographic Memory Space
♦ Security Features
Unique ID
Tamper Detection with Rapid Key/Data Destruction
Four Self-Destruct Inputs
Hardware AES and DES Engines
Public Key Cryptographic Accelerator for DSA,
ECDSA, and RSA
Real Hardware RNG and PRNG
Hardware CRC-32/16
Unalterable, Battery-Backed Real-Time Clock
♦ Additional Peripherals
Power-Fail Warning
Power-On Reset/Brownout Reset
JTAG I/F for System Programming and
Accessing On-Chip Debugger
USB I/F with Four End-Point Buffers
ISO 7816 Smart Card UART with FIFO
16-Bit Programmable Timers/Counters with
Prescaler, Capture/Compare, and PWM
SPI and USART Communication Ports
Programmable Watchdog Timer
♦ Low-Power Consumption
130nA Typical Current Draw in Battery-Backed Mode,
Preserving 8KB NV SRAM and with Security
Sensors Active (460nA with RTC Active)
Detailed Description
Refer to the full data sheet.
Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to
www.maxim-ic.com/MAXQ1850 and click on Request Full Data Sheet.
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