MB89T637PF データシートの表示（PDF） - Fujitsu
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MB89T637PF Datasheet PDF : 56 Pages
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MB89630 Series
s PRODUCT LINEUP
Part number
Parameter
MB89635
MB89636
MB89637 MB89T635 MB89T637 MB89P637 MB89W637 MB89PV630
Classification
Mass production products
(mask ROM products)
ROM size
16 K × 8
bits
(internal
mask ROM)
24 K × 8
bits
(internal
mask ROM)
32 K × 8
bits
(internal
mask ROM)
External ROM
products
Fixed to external
ROM
One-time
PROM
product
EPROM
product
32 K × 8 bits
(Internal PROM,
programming with
general-purpose
EPROM programmer)
Piggyback/
evaluation
product (for
evaluation
and
development)
32 K × 8 bits
(external
ROM)
RAM size
512 × 8 bits 768 × 8 bits
1024 × 8
bits
512 × 8
bits
1024 × 8 bits
CPU functions
Number of instructionns:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 to 6.4 µs/10 MHz, 61 µs/32.768 kHz
3.6 to 57.6 µs/10 MHz, 562.5 µs/32.768 kHz
Ports
Input ports:
Output ports (N-ch open-drain):
I/O ports (N-ch open-drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
5 (All also serve as peripherals.)
8 (All also serve as peripherals.)
4 (All also serve as peripherals.)
8 (All also serve as bus control.)
28 (27 ports also serve as bus pins and peripherals.)
53
Clock timer
8-bit PWM
timer
21 bits × 1 (in main clock)/15 bits × 1 (at 32.768 kHz)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) × 2
channels
7/8-bit resolution PWM operation (conversion cycle: 51.2 µs to 839 ms) × 2 channels
8-bit pulse
width count
timer
16-bit timer/
counter
8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit pulse width measurement operation (continuous measurement capable,
measurement of “H” pulse width/ “L” pulse width/ from ↑ to ↑/from ↓ to ↓ capable)
16-bit timer operation (operating clock cycle: 0.4 µs)
16-bit event counter operation (rising edge/falling edge/both edge selectability)
8-bit serial I/O
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
UART
Switching two I/O systems by software capable
Transfer data length (6, 7, and 8 bits)
Transfer rate (300 to 62500 bps. at 10 MHz osciliation)
10-bit A/D
converter
10-bit resolution × 8 channels
A/D conversion mode (conversion time: 13.2 µs)
Sense mode (conversion time: 7.2 µs)
Continuous activation by an external activation or an internal timer capable
(Continued)
3
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