MB90098A データシートの表示（PDF） - Fujitsu
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MB90098A Datasheet PDF : 43 Pages
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MB90098A
(2) Vertical Synchronization, Horizontal Synchronization, Display Output Control Signal Input Timing
(VDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 0 to 70 °C)
Parameter
Symbol Pin
Values
Min.
Max.
Unit Remarks
Horizontal sync signal cycle time
tHCYC HSYNC 100 + tWH
Dot clock
Horizontal sync signal pulse width
20
tWH HSYNC
Dot clock
*
6
µs
Horizontal sync signal setup time
Horizontal sync signal hold time
tDHST
4
HSYNC
tDHHD
0
ns
ns
Vertical sync signal setup time
Vertical sync signal hold time
tHVST
5
VSYNC
tHVHD
3
1H − 5
Dot clock
H
Display output control signal setup time tDDST
4
DISP
Display output control signal hold time tDDHD
0
ns
ns
Input sync signal rise-fall time
tDR
tDF
HSYNC
VSYNC
DISP
2
ns
* : During the horizontal synchronization pulse width, the MB90098A internal operations are temporarily paused
and writing to the internal VRAM is disabled. For this reason it is necessary to set both the horizontal synchro-
nization signal pulse width and the VRAM write cycle so that :
Horizontal sync signal pulse width < VRAM write cycle
Specifically, the period between instructions should be adjusted so that instruction 2 or instruction 4 (the VRAM
write instruction) is not repeated during the period of one horizontal sync signal pulse width.
If the above condition is not satisfied, writing to VRAM will not be executed normally.
• Horizontal synchronization signal, display output control signal input timing
DCLKI
0.8 VDD
0.2 VDD
HSYNC
DISP
tDHST
0.8 VDD
0.2 VDD
tDR, tDF
tDDST
0.8 VDD
0.2 VDD
tDR, tDF
tDHHD
tDDHD
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
10
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