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MB90333APFF データシートの表示(PDF) - Fujitsu

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MB90333APFF
Fujitsu
Fujitsu Fujitsu
MB90333APFF Datasheet PDF : 120 Pages
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MB90330A Series
PIN DESCRIPTION
Pin no.
Pin name
I/O
Circuit
type*
Function
108, 107
13, 14
90
X0, X1
X0A, X1A
RST
P00 to P07
93 to 100
AD00 to AD07
D00 to D07
P10 to P13
101 to 104
AD08 to AD11
D08 to D11
P14 to P17
109 to 112
AD12 to D15
D12 to D15
A
Terminals to connect the oscillator.
When connecting an external clock, leave the X1 pin side unconnected.
A 32 kHz oscillation terminals.
F External reset input pin.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1)
by the pull-up resistor setting register (RDR0). (When the power output is
set, it is invalid.)
H Function as an I/O pin for the low-order external address and data bus in
multiplex mode.
Function as an output pin for the low-order external data bus in non-
multiplex mode.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD10 to RD13 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
H Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
Function as an output pin for the high-order external data bus in non-
multiplex mode.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD14 to RD17 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
H Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
Function as an output pin for the high-order external data bus in non-
multiplex mode.
P20 to P23
113 to 116 A16 to A19
A16 to A19
This is a general purpose I/O port. When the bits of external address output
control register (HACR) are set to “1” in external bus mode, these pins
function as general purpose I/O ports.
D When the bits of external address output control register (HACR) are set to
“0” in multiplex mode, these pins function as address high output pins.
When the bits of external address output control register (HACR) are set to
“0” in non-multiplex mode, these pins function as address high output pins.
(Continued)
7

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