MB90570A データシートの表示（PDF） - Fujitsu
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MB90570A Datasheet PDF : 120 Pages
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MB90570A/570C Series
Pin no.
LQFP *1
QFP *2
7
Pin name
P37
CLK
P40
Circuit
type
E
9
F
SIN0
P41
10
F
SOT0
P42
11
F
SCK0
P43
12
F
SIN1
P44
13
F
SOT1
P45
14
F
SCK1
P46,P47
15,16
F
PPG0,PPG1
P50
17
E
SIN2
*1 : FPT-120P-M24
*2 : FPT-120P-M13, FPT-120P-M21
Function
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the clock (CLK) signal out-
put pin.
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
This is also the UART ch.0 serial data input pin. While UART ch.0 is
in input operation, this input signal is in continuous use, and therefore
the output function should only be used when needed. If shared by
output from other functions, this pin should be output disabled during
SIN operation.
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
This is also the UART ch.0 serial data output pin. This function is valid
when UART ch.0 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
This is also the UART ch.0 serial clock I/O pin. This function is valid
when UART ch.0 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to
open-drain by the ODR4 register.
This is also the UART ch.1 serial data input pin. While UART ch.1 is
in input operation, this input signal is in continuous use, and therefore
the output function should only be used when needed. If shared by
output from other functions, this pin should be output disabled during
SIN operation.
In single chip mode this is a general-purpose I/O port. It can be set to
opendrain by the ODR4 register.
This is also the UART ch.1 serial data output pin. This function is valid
when UART ch.1 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
This is also the UART ch.1 serial clock I/O pin. This function is valid
when UART ch.1 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
These are also the PPG0, 1 output pins. This function is valid when
PPG0, 1 output is enabled.
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data input pin. During serial data input,
this input signal is in continuous use, and therefore the output function
should only be used when needed.
(Continued)
DS07-13701-9E
9
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