MB91F318RPMC-G-XXXE1 データシートの表示（PDF） - Fujitsu

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MB91F318RPMC-G-XXXE1

32-bit Proprietary Microcontrollers

Fujitsu 

MB91319R Series

• Interrupt (PC, PS save) : 6 cycles, 16 priority levels

• Harvard architecture allowing program access and data access to be executed simultaneously

• Instruction prefetch function implemented by a four-word queue in the CPU

• Instruction compatible with FR family

• Bus interface

This bus interface is used for internal macro IF (USB, OSDC)

• CS1, CS2, and CS3 areas are connected as following :

CS1 area : Reserved, CS2 area : USB function, CS3 area : OSDC

• Built-in memory

Memory

RAM

Memory for program

Memory for font

MB91FV319R

48 Kbytes

Flash memory : 1 Mbyte

Flash memory : 512 Kbytes

MB91F318R/F318S

48 Kbytes

Flash memory : 1 Mbyte

MASK ROM : 384 Kbytes

MB91316/316A

32 Kbytes

MASK ROM : 512 Kbytes

MASK ROM : 384 Kbytes

• DMAC (DMA Controller)

• 5 channels (ch.0 and ch.1 are connected to USB function. )

• Two transfer sources (internal peripherals/software)

• Specifying of addressing mode 32-bit full address (increased/decreased/fixed)

• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)

• Selectable transfer data size : 8, 16, or 32-bits

• Bit search module (for REALOS)

• Search for the position of the bit “1”/“0”-changed first in one word from the MSB

• Reload timer (including a channel for REALOS)

• 16-bit timer: 3 channels

• The internal clock is selectable from 2/8/32 divisions.

• UART

• Full-duplex double buffer

• 5 channels

• Selectable parity ON/OFF

• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable

• Built-in timer for dedicated baud rate

• External clock can be used as transfer clock.

• Assorted error detection functions (for parity, frame, and overrun errors)

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