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MB91F367GA データシートの表示(PDF) - Fujitsu

部品番号
コンポーネント説明
メーカー
MB91F367GA
Fujitsu
Fujitsu Fujitsu
MB91F367GA Datasheet PDF : 62 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
1.4 Features
Function
PPG for dimmer
(4 channels)
ADC
(8 channels)
Basic Interval Timer
(3 channels)
CAN
(2 channels)
Feature
16-bit PWM Timer
16 bit down counter, cycle and duty set-
ting registers
interrupt at triggering, cycle or duty
match
can be triggered by software or reload
timer
PWM operation and one-shot operation
Remarks
Clock disable
internal prescaler allows fRES/1, fRES/4,
fRES/16, fRES/64 as counter clock
successive approximation, internal sam-
ple and hold circuit
10-bit resolution, 5 V operation,
(conversion time: 178 cycles of CLKP)
program selectable analogue input chan-
nels:
single conversion mode
continuous conversion mode
stop conversion mode
required frequencies are 90-300 Hz
interrupt at the end of a conversion can
be used to activate DMA transfer
activation by software
Prescaling is done internally
Clock disable
16-bit reload timer,
includes clock prescaler (fRES/21, fRES/23,
fRES/25)
conforms to CAN specification version
2.0 A and B
automatic re-transmission in case of
error
automatic transmission responding to
remote frame
prioritized 16 message buffers for data
and IDs
supports multiple messages
flexible configuration of acceptance filter-
ing: full bit compare / full bit mask / two
partial bit masks
supports up to 1 Mb/s
Clock Disable
CAN allows TSEG2 = RSJW setting
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 10
10-Apr-01

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