MB91F367GA データシートの表示（PDF） - Fujitsu

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MB91F367GA

32-BIT MICROCONTROLLER

Fujitsu 

External Interrupt

(8 channels)

I2C-1

for standard mode

can be programmed to be edge sensitive

or level sensitive

interrupt masking and request pending

bits per channel

master or slave transmission

arbitration function

clock synchronization function

slave address and general call address

detect function

transfer direction detect function

start condition repeat generation and

detection function

bus error detect function

Only I2C-1 or I2C-2 can be used, not

both in parallel. Bit 0 of F362MD will

be used to decide which module is

connected to the SCL and SDA

pads. By default it is I2C-1.

compatible to I2C standard mode specifi-

cation (operation up to 100 kHz,

7 bit addressing)

includes clock divider functionality

I2C-2

for standard and fast

mode

Clock disable

master or slave transmission

arbitration function

clock synchronization function

slave address and general call address

detect function

transfer direction detect function

start condition repeat generation and

detection function

bus error detect function

compatible to I2C standard and fast mode

specification (operation up to 400 kHz,

10 bit addressing)

includes clock divider functionality

Only I2C-1 or I2C-2 can be used, not

both in parallel. Bit 0 of F362MD will

be used to decide which module is

connected to the SCL and SDA

pads. By default it is I2C-1.

SCL and SDA lines include optional

noise filter. The noise filter allows

the suppression of spikes in the

range of 1 to 1.5 cycles of CLKP.

Communication on the I2C bus

between other connected devices is

not possible if MB91F36xGA is not

connected to the power supply.

Clock disable

16-bit Input Capture

(ICU)

(4 channels)

16-bit Output Compare

OCU

(2 channels)

rising edge, falling edge or rising & falling

edge sensitive

two 16-bit capture registers

signals an interrupt at external event

Clock disable

signals an interrupt when a match with

of 16-bit IO timer occurs

an output signal can be generated

Clock disable

FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 11

10-Apr-01

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