MB95107B データシートの表示（PDF） - Fujitsu

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コンポーネント説明

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MB95107B

8-bit Proprietary Microcontrollers

Fujitsu 

MB95100B Series

■ PRODUCT LINEUP

Part number

Parameter

MB95107B

MB95F108BS/

MB95F108BW

MB95R107B*3

MB95D108BS/

MB95D108BW

Type

MASK ROM

product

Flash memory

product

MASK ROM

product

Flash memory

product

ROM capacity

48K bytes

60K bytes

48K bytes

60K bytes

RAM capacity

2K bytes

FRAM capacity

No

2K bytes

Reset output

No

Clock system

Selectable

Single/Dual clock*1

Single/Dual clock*2

Selectable

Single/Dual clock*1

Single/Dual clock*2

Low voltage

detection reset

No

CPU functions

Number of basic instructions

Instruction bit length

Instruction length

Data bit length

Minimum instruction execution time

Interrupt processing time

: 136

: 8 bits

: 1 to 3 bytes

: 1, 8, and 16 bits

: 61.5 ns (at machine clock frequency 16.25 MHz)

: 0.6 µs (at machine clock frequency 16.25 MHz)

General purpose • Single clock product : 55 ports (N-ch open drain *5 : 4/6 ports, CMOS : 49 ports)

I/O ports

• Dual clock product : 53 ports (N-ch open drain *5 : 4/6 ports, CMOS : 47 ports)

Timebase timer Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)

Watchdog timer

Reset generated cycle

At main oscillation clock 10 MHz

: Min 105 ms

At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms

Wild register

Capable of replacing 3 bytes of ROM data

Master/slave sending and receiving

Bus error function and arbitration function

I2C

Detecting transmitting direction function

Start condition repeated generation and detection functions

Built-in wake-up function

UART/SIO

Data transfer capable in UART/SIO

Full duplex double buffer, Variable data length (5/6/7/8-bit), built-in baud rate generator

NRZ type transfer format, error detected function

LSB-first or MSB-first can be selected.

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

LIN-UART

Dedicated reload timer allowing a wide range of communication speeds to be set.

Full duplex double buffer.

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

LIN functions available as the LIN master or LIN slave.

8/10-bit A/D

converter

(12 channels)

8-bit or 10-bit resolution can be selected.

(Continued)

3

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