MBM29DL640E80/90/12
s FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (Dual Bank)
• FlexBankTM
Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)
Bank B : 24 Mbit (64 KB × 48)
Bank C : 24 Mbit (64 KB × 48)
Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)
Two virtual Banks are chosen from the combination of four physical banks (Refer to Table 9, 10)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimized system level power requirements
• Compatible with JEDEC-standard commands
Uses the same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)
63-ball FBGA (Package suffix : PBT)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode
Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. It also supports full chip erase.
• Hidden ROM (Hi-ROM) region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded EraseTM Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
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