M29F002 データシートの表示（PDF） - Fujitsu

部品番号

コンポーネント説明

メーカー

M29F002

2M (256K X 8) BIT FLASH MEMORY

Fujitsu 

MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90

RESET

Hardware Reset

The MBM29F002TC/BC device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low

(VIL) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset

to the read mode 20 µs after the RESET pin is driven low. If a hardware reset occurs during a program operation,

the data at that particular location will be indeterminate.

When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be

accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the

RESET pin is taken high, the device requires tRH of wake up time until outputs are valid for read access.

The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded

Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s

microprocessor to read the boot-up firmware from the Flash memory.

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