MBM29LV080A-12PTN データシートの表示（PDF） - Fujitsu

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MBM29LV080A-12PTN

8M (1M x 8) BIT

Fujitsu 

MBM29LV080A-70/-90/-12

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under

this condition. The CE circuit will partially power down the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output disable functions as described in Table 2.

The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the

DQ5 bit will indicate a “1” Please note that this is not a device failure condition since the device was incorrectly

used. If this occurs, reset the device with command sequence.

DQ3

Sector Erase Timer

After the completion of the initial Sector Erase command sequence the sector erase time-out will begin. DQ3

will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial Sector Erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may

be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept

additional Sector Erase commands. To insure the command has been accepted, the system software should

check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the

second status check, the command may not have been accepted.

See Table 8: Hardware Sequence Flags.

DQ2

Toggle Bit II

This Toggle Bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress.

For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode. (DQ2 toggles

while DQ6 does not.) See also above Table 9 and Figure 16.

Furthermore, DQ2 can also be used to determine which sector is being erased. When the devices are in the

erase mode, DQ2 toggles if this bit is read from the erasing sector.

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