MBM29LV080A-12PTN データシートの表示（PDF） - Fujitsu

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MBM29LV080A-12PTN

8M (1M x 8) BIT

Fujitsu 

MBM29LV080A-70/-90/-12

Table 8 Toggle Bit Status

Mode

Program

Erase

Erase-Suspend Read

(Erase-Suspended Sector)

(Note 1)

Erase-Suspend Program

DQ7

DQ6

DQ2

DQ7

Toggle

1

0

Toggle

Toggle

1

1

Toggle

DQ7

Toggle (Note 1)

1 (Note 2)

Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.

2. Reading the address being programmed while in the erase-suspend program mode will indicate logic “1”

at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

RY/BY

Ready/Busy Pin

The MBM29LV080A provides a RY/BY open-drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with

either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase

operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands

with the exception of the Erase Suspend command. If the MBM29LV080A is placed in an Erase Suspend mode,

the RY/BY output will be high, by means of connecting with a pull up resistor to VCC.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram. The RY/BY pin is

pulled high in stadby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

RESET

Hardware Reset Pin

The MBM29LV080A device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement

and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine. Any operation

in the process of being executed will be terminated and the internal state machine will be reset to the read mode

tREADY after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices requires an

additional tRH before it will allow read access. When the RESET pin is low, the device will be in the standby mode

for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a

program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY

output signal should be ignored during the RESET pulse. See Figure 12 for the timing diagram. Refer to Tem-

porary Sector Unprotection for additional functionality.

If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)

cannot be used.

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