MBM29PL160BD データシートの表示（PDF） - Fujitsu

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MBM29PL160BD

16M (2M × 8/1M × 16) BIT

Fujitsu 

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

MBM29PL160BD = 45H for ×8 mode; MBM29PL160TD = 2227H and MBM29PL160BD = 2245H for ×16 mode).

(See Tables 4.1 and 4.2.)

All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit.

The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8).

Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce

a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin

mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,

also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command

sequence.

Word/Byte Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.

Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the

rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system

is not required to provide further controls or timings. The device will automatically provide adequate internally

generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the device return to the read mode and addresses are no longer latched. (See Table 9, Hardware

Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.

Hence, Data Polling must be performed at the memory location which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occures during the

programming operation, it is impossible to guarantee whether the data being written is correct or not.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 16 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the device will automatically program and verify the entire memory for an all zero

data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls

or timings during these operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates

when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read mode.

(See Figure 8.)

Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”

command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address

(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data

= 30H) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase

command, the sector erase operation will begin.

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