MC100E446FNR2 データシートの表示（PDF） - ON Semiconductor
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MC100E446FNR2 Datasheet PDF : 12 Pages
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MC10E446, MC100E446
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9)
0°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
FMAX Max Conversion Frequency
1.3 1.6
1.3 1.6
1.3 1.6
Gb/s
NRZ
tPLH
Propagation Delay to Output
ps
tPHL
CLK to SOUT (Note 10) 1020 1200 1480 1020 1200 1480 1020 1200 1480
CLK to CL/4 650 850 1050 650 850 1050 650 850 1050
CLK to CL/8 800 1050 1300 800 1050 1300 800 1050 1300
SYNC to CL/4, CL/8 650 850 1100 650 850 1100 650 850 1100
ts
Setup Time (Note 11)
SIN, Dn -200 -450
-200 −450
−200 −450
ps
th
Hold Time (Note 11)
SIN, Dn 900 650
900 650
900 650
ps
tRR
Reset Recovery Time
SYNC 500 300
500 300
500 300
ps
tPW
Min Pulse Width
CLK, MR 300
300
300
ps
tJITTER Random Clock Jitter (RMS)
<1
<1
<1
ps
VPP
Input Voltage Swing (Differential Configuration)
150
1000 150
1000 150
1000 mV
tr
Rise/Fall Times (20% - 80%)
tf
Other
SOUT 100 225 350 100 225 350 100 225 350 ps
200 425 650 200 425 650 200 425 650
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
10. Propagation delays measured from negative going clock edge.
11. Relative to negative clock edge.
CLK
ÉÉÉÉD ÉÉÉÉSÉÉÉÉetupÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Valid DataÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉHoldÉÉÉÉÉÉÉÉÉÉÉÉ
SYNC
trr
ts
th
CLK
Figure 3.
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