MC100LVEL05 データシートの表示（PDF） - ON Semiconductor

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MC100LVEL05

3.3V ECL 2-Input Differential AND/NAND

ON Semiconductor 

D0 1

D0 2

D1 3

D1 4

MC100LVEL05

8 VCC

7Q

6Q

5 VEE

Table 1. PIN DESCRIPTION

PIN

FUNCTION

D0, D0; D1, D1

Q, Q

VCC

VEE

EP

ECL Data Inputs

ECL Data Outputs

Positive Supply

Negative Supply

Exposed pad must be con-

nected to a sufficient thermal

conduit. Electrically connect

to the most negative supply or

leave floating open.

Figure 1. Logic Diagram and Pinout Assignment

Table 2. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

VCC

PECL Mode Power Supply

VEE

NECL Mode Power Supply

VI

PECL Mode Input Voltage

NECL Mode Input Voltage

Iout

Output Current

VEE = 0 V

VCC = 0 V

VEE = 0 V

VCC = 0 V

Continuous

Surge

VI  VCC

VI  VEE

8 to 0

V

−8 to 0

V

6 to 0

V

−6 to 0

V

50

mA

100

mA

TA

Operating Temperature Range

Tstg

Storage Temperature Range

qJA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 SOIC

8 SOIC

−40 to +85

−65 to +150

190

130

°C

°C

°C/W

°C/W

qJC

Thermal Resistance (Junction−to−Case)

Standard Board

8 SOIC

qJA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 TSSOP

8 TSSOP

41 to 44 ± 5%

185

140

°C/W

°C/W

°C/W

qJC

Thermal Resistance (Junction−to−Case)

Standard Board

8 TSSOP

qJA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

DFN8

41 to 44 ± 5%

129

84

°C/W

°C/W

°C/W

Tsol

Wave Solder

Pb <2 to 3 sec @ 248°C

Pb−Free <2 to 3 sec @ 260°C

265

°C

265

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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