MC100LVELT22(2016) データシートの表示（PDF） - ON Semiconductor

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MC100LVELT22
(Rev.:2016)

Translator, Dual LVTTL / LVCMOS to Differential LVPECL

ON Semiconductor 

MC100LVELT22

Figure 2. Typical MC100LVELT22 Phase Noise Plot at fCarrier = 50 MHz, VCC = 3.3 V, 255C

The above phase noise data was captured using Agilent

E5052A/B. The data displays the input phase noise and

output phase noise used to calculate the additive phase jitter

at a specified integration range. The additive RMS phase

jitter contributed by the device (integrated between 12 kHz

and 20 MHz) is 219 fs. The additive RMS phase jitter

performance of the translator is highly dependent on the

phase noise of the input source.

To obtain the most precise additive phase noise

measurement, it is vital that the source phase noise be

notably lower than that of the DUT. If the phase noise of the

source is greater than the noise floor of the device under test,

the source noise will dominate the additive phase jitter

calculation and lead to an incorrect negative result for the

additive phase noise within the integration range. The

Figure above is a good example of the MC100LVELT22

source generator phase noise having a significantly lower

floor than the DUT and results in an additive phase jitter of

219 fs.

Additive RMS phase jitter = √RMS phase jitter of output2 − RMS phase jitter of input2

219 fs + Ǹ587.92 fs2 * 545.23 fs2

Figure 2 was created with measured data from

Agilent−E5052B Signal Source Analyzer using ON

Semiconductor Phase Noise Explorer web tool. This free

application enables an interactive environment for advanced

phase noise and jitter analysis of timing devices and clock

tree designs. To see the performance of MC100LVELT22

beyond conditions outlined in this datasheet, please visit the

ON Semiconductor Green Point Design Tools homepage.

www.onsemi.com

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