MC100E016FNG データシートの表示（PDF） - ON Semiconductor

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MC100E016FNG

5.0 VECL 8−Bit Synchronous Binary Up Counter

ON Semiconductor 

MC10E016, MC100E016

PE CE P7 P6 P5 VCCO TC

25 24 23 22 21 20 1

MR 26

9 18 Q7

CLK 27

17 Q6

TCLD 28

VEE 1

16 VCC

15 Q5

NC 2

14 VCCO

P0 3

13 Q4

P1 4

12 Q3

5 6 7 8 9 10 11

P2 P3 P4 VCCO Q0 Q1 Q2

All VCC and VCCO pins are tied together on the die.

Warning: All VCC, VCCO, and VEE pins must be externally

connected to Power Supply to guarantee proper operation.

Figure 1. 28−Lead Pinout Assignment (Top View)

PE

Table 1. PIN DESCRIPTION

PIN

FUNCTION

P0 − P7

Q0 − Q7

CE

PE

MR

CLK

TC

TCLD

NC

VCC, VCCO

VEE

ECL Parallel Data (Preset) Inputs

ECL Data Outputs

ECL Count Enable Control Input

ECL Parallel Load Enable Control Input

ECL Master Reset

ECL Clock

ECL Terminal Count Output

ECL TC−Load Control Input

No Connect

Positive Supply

Negative Supply

Q0

Q1

Q7

TCLD

CE

Q0M

MASTER

Q0M

SLAVE

Q0

CE

BIT 1

BIT 0

CQE1 QQ02

Q4

Q3

Q5

Q6

PO

P1

P7

MR

CLK

Note that this diagram is provided for understanding of

logic operation only. It should not be used for propagation

delays as many gate functions are achieved internally

without incurring a full gate delay.

BITS 2−6

5

Figure 2. 8−Bit Binary Counter Logic Counter

Table 2. FUNCTION TABLE

FUNCTION

Load Parallel (Pn to Qn)

Continuous Count

Count; Load Parallel on TC = LOW

Hold

Masters Respond, Slaves Hold

Reset (Qn : = LOW, TC : = HIGH)

Z = clock pulse (low to high);

ZZ = clock pulse (high to low)

CE PE TCLD MR CLK

XL

X

LZ

LH

L

LZ

LH

H

L

Z

HH

X

LZ

XX

X

L ZZ

XX

X

HX

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2

BIT 7

TC

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