MC100E016FNG データシートの表示（PDF） - ON Semiconductor

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MC100E016FNG

5.0 VECL 8−Bit Synchronous Binary Up Counter

ON Semiconductor 

MC10E016, MC100E016

APPLICATIONS INFORMATION (continued)

Programmable Divider

The E016 has been designed with a control pin which

makes it ideal for use as an 8−bit programmable divider. The

TCLD pin (load on terminal count) when asserted reloads

the data present at the parallel input pin (Pn’s) upon reaching

terminal count (an all 1s state on the outputs). Because this

feedback is built internal to the chip, the programmable

division operation will run at very nearly the same frequency

as the maximum counting frequency of the device. Figure 4

below illustrates the input conditions necessary for utilizing

the E016 as a programmable divider set up to divide by 113.

HL L L HHHH

P7 P6 P5 P4 P3 P2 P1 P0

H PE

L CE

H TCLD

TC

CLK

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Figure 4. Mod 2 to 256 Programmable Divider

To determine what value to load into the device to

accomplish the desired division, the designer simply

subtracts the binary equivalent of the desired divide ratio

from the binary value for 256. As an example for a divide

ratio of 113:

Pn’s = 256 − 113 = 8F16 = 1000 1111

where:

P0 = LSB and P7 = MSB

Forcing this input condition as per the setup in Figure 4

will result in the waveforms of Figure 5. Note that the TC

output is used as the divide output and the pulse duration is

equal to a full clock period. For even divide ratios, twice the

desired divide ratio can be loaded into the E016 and the TC

output can feed the clock input of a toggle flip flop to create

a signal divided as desired with a 50% duty cycle.

Table 11. Preset Values for Various Divide Ratios

Divide

Ratio

Preset Data Inputs

P7 P6 P5 P4 P3 P2 P1 P0

2

HHHHHHH L

3

HHHHHH L H

4

HHHHHHL L

5

HHHHH L HH

w

w• • • • • • •

w

••••••••

112

HL LHLLL L

113

HL L LHHHH

114

HL L LHHH L

•

••••••••

•

••••••••

254

LL LLLLHL

255

L L L L L L LH

256

LLLLLLLL

A single E016 can be used to divide by any ratio from 2

to 256 inclusive. If divide ratios of greater than 256 are

needed multiple E016s can be cascaded in a manner similar

to that already discussed. When E016s are cascaded to build

larger dividers the TCLD pin will no longer provide a means

for loading on terminal count. Because one does not want to

reload the counters until all of the devices in the chain have

reached terminal count, external gating of the TC pins must

be used for multiple E016 divider chains.

Clock

PE

Load

1001 0000 1001 0001 1111 1100 1111 1101 1111 1110

1111 1111

Load

•••

•••

•••

TC

DIVIDE BY 113

Figure 5. Divide by 113 E016 Programmable Divider Waveforms

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