MC100E195 データシートの表示（PDF） - ON Semiconductor
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MC100E195 Datasheet PDF : 11 Pages
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MC10E195, MC100E195
Table 8. AC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 1))
0°C
25°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
fMAX
tPLH
tPHL
Maximum Toggle Frequency
Propagation Delay
IN to Q; Tap = 0
IN to Q; Tap = 127
EN to Q; Tap = 0
D7 to CASCADE
> 1.0
1210
3200
1250
300
1360
3570
1450
450
1510
3970
1650
700
1240
3270
1275
300
1390
3630
1475
450
1540
4030
1675
700
1440
3885
1350
300
85°C
Typ
1590
4270
1650
450
Max
1765
4710
1950
700
Unit
GHz
ps
tRANGE
Dt
Lin
tSKEW
tJITTER
ts
Programmable Range
tPD (max)−tPD (min)
Step Delay (Note 2)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
Linearity (Note 3)
Duty Cycle Skew
tPHL−tPLH (Note 4)
Random Clock Jitter (RMS)
Setup Time
D to LEN
D to IN (Note 5)
EN to IN (Note 6)
ps
2000 2175
2050 2240
2375 2580
ps
17
17.5
21
34
35
42
55
68 105 55
70 105 65
84 120
115 136 180 115 140 180 140 168 205
250 272 325 250 280 325 305 336 380
505 544 620 515 560 620 620 672 740
1000 1088 1190 1030 1120 1220 1240 1344 1450
D1 D0
D1 D0
D1 D0
ps
±30
±30
±30
<5
<5
<5
ps
ps
200
0
200
0
200
0
800
800
800
200
200
200
th
Hold Time
LEN to D
IN to EN (Note 7)
tR
Release Time
EN to IN (Note 8)
SET MAX to LEN
SET MIN to LEN
ps
500 250
500 250
500 250
0
0
0
ps
300
300
300
800
800
800
800
800
800
tjit
Jitter
tr
Output Rise/Fall Time
tf
20−80% (Q)
20−80% (CASCADE)
<5
<5
<5
ps
ps
125 225 325 125 225 325 125 225 325
300 450 650 300 450 650 300 450 650
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
2. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
3. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the
Least Significant Bit (LSB), the device is guaranteed to be monotonic over all specified environmental conditions and process variation.
4. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
5. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
6. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
7. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
8. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
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