MC10H117MEL データシートの表示（PDF） - ON Semiconductor
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MC10H117MEL Datasheet PDF : 6 Pages
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MC10H117
Dual 2−Wide 2−3−Input
OR−AND/OR−AND Gate
Description
The MC10H117 dual 2−wide 2−3−input OR−AND/
OR−AND−Invert gate is a general purpose logic element designed for
use in data control, such as digital multiplexing or data distribution.
Pin 9 is common to both gates. This MECL 10H™ part is a
functional/pinout duplication of the standard MECL 10K™ family
part, with 100% improvement in propagation delay, and no increase in
power−supply current.
Features
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 100 mW/Gate Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K Compatible
• Pb−Free Packages are Available*
http://onsemi.com
MARKING DIAGRAMS*
CDIP−16
L SUFFIX
CASE 620A
16
MC10H117L
AWLYYWW
1
16
16
1
PDIP−16
P SUFFIX
CASE 648
MC10H117P
AWLYYWWG
1
10H117
ALYWG
SOEIAJ−16
CASE 966
1 20
20 1
PLLC−20
FN SUFFIX
CASE 775
10H117G
AWLYYWW
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
February, 2006 − Rev. 7
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC10H117/D
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