NLV14018BDG データシートの表示（PDF） - ON Semiconductor
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NLV14018BDG Datasheet PDF : 5 Pages
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MC14018B
1
CLOCK
0
1
RESET
0
PRESET ENABLE
1
0
1
JAM 1
0
JAM 2
1
0
TIMING DIAGRAM
(Q5 Connected to Data Input)
JAM 3
DON'T CARE
UNTIL PRESET ENABLE
GOES HIGH
1
0
1
JAM 4
0
1
JAM 5
0
1
Q1
0
1
Q2
0
Q3
1
0
1
Q4
0
1
Q5
0
FUNCTION SELECTION
Counter
Mode
Connect
Data Input
(Pin 1) to:
Comments
Divide by 10
Q5
Divide by 8
Divide by 6
Divide by 4
Q4
Q3
Q2
No external
components needed.
Divide by 2
Q1
Divide by 9
Divide by 7
Divide by 5
Divide by 3
Q5 • Q4
Q4 • Q3
Q3 • Q2
Q2 • Q1
Gate package needed
to provide AND
function. Counter
Skips all 1’s state
JAM 1
2
LOGIC DIAGRAM
JAM 2
3
JAM 3
7
JAM 4
9
JAM 5
12
CLOCK 14
DATA 1
RESET 15
PRESET ENABLE 10
CLOCK
SHAPER
D SQ
C
RP
D SQ
C
Q
RP
D SQ
C
RP
D SQ
C
RP
D SQ
C
RP
VDD = PIN 16
VSS = PIN 8
5
4
Q1
Q2
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4
6
11
Q3
Q4
13
Q5
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