MC141541 データシートの表示（PDF） - Motorola => Freescale
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MC141541 Datasheet PDF : 16 Pages
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Display Register
REGISTERS
ÎÎCÎÎC7S0ÎÎ6ÎÎÎÎ5 ÎÎ4 ÎÎÎÎ3 ÎÎ2 ÎÎ1ÎÎÎÎ0ÎÎ
CRADDR
Bit 7 CCS0 — This bit defines a specific character color
out of the two preset colors. Color 1 is selected if this bit is
cleared, and Color 2 otherwise.
Bit 6–0 CRADDR — These seven bits address the 128
characters or symbols residing in the character ROM.
Row Control Registers
7
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN30 R1
Coln 30
6 54 32 1
0
G1 B1 R2 G2 B2 CHS CWS
Bits 7–2 — Color 1 is determined by R1, G1, and B1; Color
2 by R2, G2, and B2.
Bit 1 CHS — This bit determines the height of a display
symbol. When it is set, the symbol is displayed in double
height.
Bit 0 CWS — Bit 0 is similar to Bit 1; when this bit is set, the
character is displayed in double width.
Coln 31
7
6
54
32
1
0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN31 R3 G3 B3 R4 G4 B4
Bits 7–2 — Color 3 is determined by R3, G3, and B3; Color
4 by R4, G4, and B4.
Window 1 Registers
Row 10 Coln 0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ROW 10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN 0
76
5432
10
ROW START ADDR
ROW END ADDR
MSB
LSB MSB
LSB
Row 10 Coln 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ROW 10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN 1
7
6
5432
1
0
COL START ADDR
MSB
LSB
WEN CCS1 HPOL
Bit 2 WEN — This bit enables the background Window 1
generation when it is set.
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 1 with two extra color
selections, making a total of four selections for that row.
Bit 0 HPOL — This bit selects the polarity of the incoming
horizontal sync signal (HFLB) on Pin 5. If it is negative polar-
ity, clear this bit. Otherwise, set this bit to 1 to represent the
positive H sync signal. After power–on, this bit is cleared.
Row 10 Coln 2
76
5432
ÎÎÎÎÎÎÎÎÎÎÎÎ ROW 10
COL END ADDR
ÎÎÎÎÎÎÎÎÎÎÎÎ COLN2 MSB
LSB R
10
GB
Bits 2–0 R, G and B — These bits control the color of Win-
dow 1. Window 1 occupies Columns 0–2 of Row 10; Window
2 occupies Columns 3–5; and Window 3 occupies Columns
6–8. Window 1 has the highest priority, and Window 3 the
least. If window overlapping occurs, the higher priority win-
dow will cover the lower one, and the higher priority color will
take over on the overlap window area. If the start address is
greater than the end address, this window will not be dis-
played.
Window 2 Registers
Row 10 Coln 3
76
5432
10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ROW 10
ROW START ADDR
ROW END ADDR
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN3 MSB
LSB MSB
LSB
Row 10 Coln 4
ROW 10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN 4
76
54
COL START ADDR
MSB
32
10
LSB WEN CCS1 VPOL
Bit 2 WEN — This bit enables the background Window 2
generation when it is set.
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 2 with two extra color
selections, making a total of four selections for that row.
Bit 0 VPOL — This bit selects the polarity of the incoming
vertical sync signal (VFLB) on Pin 5. If it is negative polarity,
clear this bit. Otherwise, set this bit to 1 to represent the posi-
tive V sync signal. After power–on, this bit is cleared.
Row 10 Coln 5
76
5432
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ROW 10
COL END ADDR
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN5 MSB
LSB R
10
GB
Bit 2–0 R, G and B — These bits control the color of Win-
dow 2. Window 1 occupies Columns 0–2 of Row 10; Window
2 occupies Columns 3–5; and Window 3 occupies Columns
6–8. Window 1 has the highest priority, and Window 3 the
least. If window overlapping occurs, the higher priority win-
dow will cover the lower one, and the higher priority color will
take over on the overlap window area. If the start address is
greater than the end address, this window will not be dis-
played.
Window 3 Registers
Row 10 Coln 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ROW 10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN 6
76
5432
10
ROW START ADDR
ROW END ADDR
MSB
LSB MSB
LSB
MC141541
8
MOTOROLA
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