MC14511B データシートの表示（PDF） - ON Semiconductor

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MC14511B

BCD−To−Seven Segment Latch/Decoder/Driver

ON Semiconductor 

MC14511B

Input LE low, and Inputs D, BI and LT high.

f in respect to a system clock.

All outputs connected to respective CL loads.

20 ns

A, B, AND C

20 ns

90%

VDD

50%

1

10%

2f

VSS

50% DUTY CYCLE

VOH

50%

ANY OUTPUT

VOL

Figure 1. Dynamic Power Dissipation Signal Waveforms

20 ns

INPUT C

tPLH

OUTPUT g

50%

tTLH

90%

50%

10%

tPHL

90%

20 ns

VDD

VSS

VOH

10%

VOL

tTHL

(a) Inputs D and LE low, and

Inputs A, B, BI and LT high.

20 ns

90%

VDD

LE

50%

10%

th

VSS

tsu

VDD

INPUT C

50%

VSS

VOH

OUTPUT g

VOL

(b) Input D low,

Inputs A, B, BI and LT high.

20 ns

90%

LE

50%

10%

tWL

20 ns

VDD

VSS

(c) Data DCBA strobed into latches.

Figure 2. Dynamic Signal Waveforms

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