MC14526B(2000) データシートの表示（PDF） - ON Semiconductor
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MC14526B Datasheet PDF : 12 Pages
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MC14526B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Symbol
VDD
Min
Typ (8.)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
—
100
200
(Figures 4, 5)
10
—
50
100
15
—
40
80
Propagation Delay Time (Inhibit Used as Negative
tPLH,
ns
Edge Clock)
tPHL
Clock or Inhibit to Q
(Figures 4, 5, 6)
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns
5.0
—
550
1100
10
—
225
450
15
—
160
320
Clock or Inhibit to “0”
tPLH, tPHL = (1.7 ns/pF) CL + 155 ns
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
5.0
—
240
480
10
—
130
260
15
—
100
200
Propagation Delay Time
Pn to Q
tPLH,
5.0
—
260
520
ns
tPHL
10
—
120
240
(Figures 4, 7)
15
—
100
200
Propagation Delay Time
Reset to Q
tPHL
5.0
—
250
500
ns
10
—
110
220
(Figure 8)
15
—
80
160
Propagation Delay Time
Preset Enable to “0”
tPHL,
5.0
—
220
440
ns
tPLH
10
—
100
200
(Figures 4, 9)
15
—
80
160
Clock or Inhibit Pulse Width
tw
5.0
10
(Figures 5, 6)
15
250
125
100
50
80
40
—
ns
—
—
Clock Pulse Frequency (with PE = low)
fmax
5.0
—
2.0
1.5
MHz
10
—
5.0
3.0
(Figures 4, 5, 6)
15
—
6.6
4.0
Clock or Inhibit Rise and Fall Time
tr,
5.0
—
—
15
µs
tf
10
—
—
5
(Figures 5, 6)
15
—
—
4
Setup Time
Pn to Preset Enable
tsu
5.0
90
40
—
ns
10
50
15
—
(Figure 10)
15
40
10
—
Hold Time
Preset Enable to Pn
th
5.0
10
(Figure 10)
15
30
– 15
—
ns
30
–5
—
30
0
—
Preset Enable Pulse Width
tw
5.0
10
(Figure 10)
15
250
125
100
50
80
40
—
ns
—
—
Reset Pulse Width
tw
5.0
350
175
—
ns
10
250
125
—
(Figure 8)
15
200
100
—
Reset Removal Time
trem
5.0
10
– 110
—
ns
10
20
– 30
—
(Figure 8)
15
30
– 20
—
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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